The present invention relates to semiconductor manufacturing processes. In particular, embodiments of the present invention relate to a method for forming shallow trench isolation (STI) structures.
In semiconductor manufacturing processes, shallow trench isolation (STI) structures are critical to the final performance of the electrical properties of semiconductor devices. In forming shallow trench isolation structures, the trenches are often filled with dielectrics, for example, using a high aspect ratio process (HARP). Due to loading effects during in the filling process, the quality of the HARP dielectric may be different in different regions in the semiconductor substrate. As a result, the wet etch rate (WER) of a subsequent wet cleaning process, such as dilute hydrofluoric acid (DHF), may be different, thus resulting in height variations in the shallow trench isolation structures over the semiconductor substrate.
FIG. 1 is a cross-sectional diagram illustrating shallow trench isolation structures formed in a substrate 100 using a conventional method. In FIG. 1, shallow trench isolation structures 101 are formed in a region of dense patterns, and a shallow trench isolation structure 102 is formed in a region of less dense or isolated patterns. It can be seen that the height 103 of shallow trench isolation structures 101 is lower than the height 104 of shallow trench isolation structure 102. One explanation is that the width of STI structures 101 in a dense region is narrower than the width of STI structure 102 formed in a less dense region. As a result, more severe loading effect is shown in the filling of shallow trench isolation structure 101 compared with the shallow trench isolation structure 102. During subsequent wet cleaning processes, the wet etch rate of DHF cleaning solution is higher in shallow trench isolation structure 101 compared with the shallow trench isolation structure 102, leading to variations in the height of STI structures.
Due to the non-uniform height of the shallow trench isolation structures, height variations also exist in subsequently formed gate dielectric material layer and gate electrode material. These variations can lead to different electrical properties in devices formed in different regions of the semiconductor substrate.
Therefore, it is desirable to have an improved method for forming STI structures and resolve the problems described above.